The present invention relates to non-volatile memory devices and, more particularly, to a method of manufacturing a non-volatile memory device with a reduced step between a cell region and a peripheral region.
In general, a non-volatile memory device does not lose information even though the supply of power is turned off. Non-volatile memory devices generally include Electrically Programmable Read Only Memory (EPROM), Electrically Erasable and Programmable Read Only Memory (EEPROM), flash EEPROM and so on. In recent years, memory has been formed to have a Silicon/Oxide/Nitride/Oxide/Silicon (SONOS) structure having a three-layered gate insulating layer of an oxide layer/a nitride layer/an oxide layer. If this SONOS structure is used, a non-volatile memory device with low voltage, low consumption power, and high-speed operation can be manufactured. It can also increase the level of integration in devices. The operating principle of the non-volatile memory device having this SONOS structure is described below.
The non-volatile memory device of the SONOS structure utilizes the electrical potential difference between an oxide layer and a nitride layer. Electrons trapped at the nitride layer are not lost due to a potential barrier formed by the underlying and overlaying oxide layers although power is off, and maintains its non-volatile property. Programming is performed by applying a voltage through which electrons can tunnel the thin oxide layer existing below the nitride layer, and reading is carried out by discriminating the driving current difference caused by the difference in transistor threshold voltage using a differential amplifier.
Meanwhile, in order to implement this SONOS structure, before the dielectric layer of the three-layered structure is formed in a cell region, a gate insulating layer and a polysilicon layer are formed in a peripheral region. That is, a cell gate including a dielectric layer and a conductive layer is formed in the cell region, and a gate including the gate insulating layer, the polysilicon layer, a dielectric layer and a conductive layer is formed in the peripheral region. The gate formed in the peripheral region includes the polysilicon layer, so that a step due to the polysilicon layer is generated between the cell region and the peripheral region. A SAC nitride layer and an interlayer insulating layer are formed over a semiconductor substrate including the cell gate and the gate. A polishing process is performed on the interlayer insulating layer. The SAC nitride layer formed over the gate of the peripheral region is exposed anterior to the SAC nitride layer formed over the cell gate of the cell region due to the step. For this reason, the SAC nitride layer formed over the gate of the peripheral region can be removed during the polishing process. It results in an increased leakage current of a high voltage transistor of the peripheral region. Furthermore, a hump characteristic is generated due to the leakage current, and malfunction of the high voltage transistor may occur due to variation in the threshold voltage of the high voltage transistor.